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TMB2193MS100
Demonstration Board for the TMC2193
Features
* * * * * * 10-bit or 20-bit Parallel YCbCr input 24-bit RGB input D1, Genlock and Master mode operation Composite, S-video and component analog outputs Digital Composite output Fairchild demo board compatibility
Description
The TMB2193MS100 demonstration board provides a flexible base for evaluating the performance of the TMC2193 Digital Video Encoder (DENC). The demonstration board can be driven by either a D1 or Genlock signal, or it can supply the synchronization signals needed to drive a framestore or any MPEG Decoder. Both YCbCr, in either 4:2:2, D1, or 4:4:4 formats, and RGB inputs are supported. The board provides high quality analog composite video, analog S-video, analog component video and digital composite video outputs.
Preliminary Information
Applications
* * * * Evaluation of TMC2193 DENC Evaluation of TMC2072 Genlock interface Output for TMC2068P7C Decoder demo board System Breadboarding
Block Diagram
RBUS Connector +5V 0V -5V 96 Way Edge Connector (female) Digital Inputs: 10 bit D1 24 bit RGB 20 bit YCbCr PXCK TMC2193 Digital Outputs: 32 HSYNC VSYNC MPXCK Analog LPF Digital Outputs (Optional): 10 bit DCVBS HSYNC VSYNC PXCK
65-B2193-01
1
FPGA
MCU
TMC2072
Analog Outputs: Composite S-Video RGB YPbPr Sync
Rev. 0.9.0
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
TMB2193MS100
PRODUCT SPECIFICATION
Functional Description
The TMB2193MS100 is designed to demonstrate the performance of the TMC2193 Digital Video Encoder (DENC). For a complete description of the TMC2193, please refer to the TMC2193 data sheet. The TMB2193MS100 is compatible with other Fairchild Demo boards. Typical configurations are the TMC2067P7C, the TMC2068P7C, and the TMB2193MS100 or the TMB0001MS100 and the TMB2193MS100. The first configuration requires an analog composite or S-video input and supplies a re-encoded analog composite or S-video output. The later requires a parallel D1 input and supplies an encoded analog composite or S-video output.
the TMC2193, supplying the line (HSYNC) and field (VSYNC or BnT) synchronization signals. With the TMC2193 running in Master mode the TMB2193MS100 demo board interfaces directly to either a MPEG decoder or a video framestore with no additional glue logic. The TMB2193MS100 has an onboard microcontroller (MCU) to program the TMC2193, the TMC2072, and to configure the FPGA. All the default register maps are held within the MCU. Table 1 provides a description of each of the default register maps. A control register map is written to the TMC2193, the TMC2072, and to Port 2 of the MCU each time the MRST\ button is pressed. The MCU determines which map to load from the PROG[3-0] (Px) dip switches. The TMC2193, 2072 and the MCU can also be driven by the Raydemo software. The interface is provided by the RBUS connector on the TMB2193MS100 and the TMC2070P7C R-Bus interface board. With this setup the user can configure the TMC2193, the TMC2072 and the MCU with any IBM compatible PC.
Preliminary Information
The TMC2193 can be operated in D1, Genlock or Master mode. In the D1 mode the synchronization is derived from the TRS codes embedded in the D1 data stream. The TMB2193MS100 has the TMC2072 Genlock front end, which supplies the HSYNC, VSYNC and subcarrier information to the TMC2193 for the Genlock operation of the encoder. In Master mode the synchronization is driven by Table 1. Default Control Register Maps P3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 P2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 P1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 P0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Format NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC PAL PAL PAL PAL PAL PAL PAL PAL Mode MASTER MASTER MASTER D1 D1 D1 Genlock Genlock MASTER MASTER MASTER D1 D1 D1 Genlock Genlock
Source Mod. Ramp 75% CB 100% CB D1 D1 D1 601 601 Mod. Ramp 75% CB 100% CB D1 D1 D1 601 601
Output Mode Composite, S-Video Composite, YPBPR Composite, RGB Composite, YPBPR Composite, RGB DCVBS Composite, YPBPR Composite, RGB Composite, S-Video Composite, YPBPR Composite, RGB Composite, YPBPR Composite, RGB DCVBS Composite, YPBPR Composite, RGB
2
PRODUCT SPECIFICATION
TMB2193MS100
CPLD Description
The Altera 10K20 CLPD functions as the central matrix for routing the buses to the TMC2193. Eight (8) control pins are connected from port 2 of the MCU to the CLPD. These pins are used to configure the CPLD and are broken up into 2 buses: FPGA control1 is on pins P2[7:4] and FPGA control2 is on pins P2[3:0]. The 10K20 default configuration routes the 3 buses from the input edge connector and the bus from the framestore header to the pixel data (PD[23:0]) port of the TMC2193. This enables the various input formats of the TMC2193 to be supported. In addition, the PD input can be delayed in respect to the HSIN and VSIN for proper data alignment. Table 2 describes the function of the pixel data formatting. Table 2. FPGA Control 1 FGPA Control1 bit# 3-2
The FPGA Control 2 bus selects which subcarrier reference signal to be used; either the GRS from the TMC2072 or the xRS signal from bus B of the input edge connector. FGPA Control 2 also selects which set of synchronization signals are to used; either the IXHSYNC and IXVSYNC from the input edge connector or the TMC2072 GHSYNC and GVSYNC. Table 3. FPGA Control 2 FGPA Control2 bit# 3-2 1 REFSEL 0 1 0 SYNCSEL 0 1 Function Description No Modes CVBS Input B[5:2] bus GENLOCK HSIN, VSIN Input IXH and IXV GH and GV
Preliminary Information
Function PDMODE 00 01 10 11
Description PD Input 10-bit format, A bus 20-bit format, C and B buses 24-bit format, C, A, and B buses 10-bit format, A bus delayed PD delay 0 pxck's of delay 1 pxck's of delay 2 pxck's of delay 3 pxck's of delay
FPGA Controls 1 and 2 can be accessed by the Raydemo software. The dialog box exists in the MCU icon of the TMB2193MS100 window. The functions of these controls are purposely left generic to allow for the reconfiguration of the CPLD. The 10K20 utilization is approximately 20% of the available logic cells. This allows for additional functions to be implemented in the 10K20 such as notch filters, interpolation filters for 4:2:2 to 4:4:4 conversion, simple comb filtering and ancillary data insertion. These are just some of the possibilities.
1-0
PDDEL 00 01 10 11
Table 4. Switch, Button, and Jumper Description Button MRST Jumpers GLOBAL RESET Description Resets the AT89C55. When the GLOBAL RESET jumper is in place, the reset line on all boards connected to the TMB2193MS100 are driven by MRST. Description When GLOBAL RESET is open, only the TMC2193, the TMC2072, the framestore header and the AT89C55 receive the reset pulse from MRST. When GLOBAL RESET is closed, the reset line on all boards connected to the TMB2193MS100 are driven by MRST. Cascade Programming Enable. When CASC INT is open, the AT89C55 automatically initializes the devices after reset. When CASC INT is closed, the AT89C55 will wait for a LOW pulse on the PGM_IN pin before initializing the devices on the TMB2193MS100. RBUSEN When RBUSEN is open, the RBUS port is disabled. When RBUSEN is closed, the RBUS port is enabled.
CASC INT
3
TMB2193MS100
PRODUCT SPECIFICATION
Table 4. Switch, Button, and Jumper Description (continued) Button JP20, JP21, JP22, JP23 Switches E1 E2 Description When JPx is open, the output video is a single 75Ohm termination. When JPx is closed, the output video is a double 75Ohm termination. Description Onboard Clock Selection. Selects either the PXCK from the TMC2072 or the onboard TTL clock oscillator. Master Clock Selection. When Pass is selected the clock source for the entire board is either the TMC2072 PXCK or the TTL clock oscillator. When IXPCK is selected the clock source for the entire board is the PXCK from the input header. E3 Dip Switches SA1-0 CAS ERS P3-0 Output Header Clock Selection. Selects either PXCK or PXCK for the output header. Description Configures the bits 2 and 1 of the TMC2193 RBUS chip address. When SAx is ON (down), ESAx is in a LOW state. When SAx is OFF (up), ESAx is in a HIGH state. Configures the bit 2 of the TMC2072 RBUS chip address. When CAS is ON (down), GSA1 is in a LOW state. When CAS is OFF (up), GSA1 is in a HIGH state. Configures the bit 1 of the TMC2072 RBUS chip address. When ERS is ON (down), GSA0 is in a LOW state. When ERS is OFF (up), GSA0 is in a HIGH state. Control Register Programming. P3-0 selects which control register map to configure the devices with. Refer to Table 1 Default Control Register Maps for a description.
Preliminary Information
Setup Procedure
Set E1 to MPXCK and E2 to PASS, enable the onboard TTL clock oscillator as the clock source. 1. 2. 3. Set ESA1-0 to ON (down). Set P3-0 to 0h, P3 is ON (down), P2 is ON (down), P1 is ON (down), and P0 is ON (down). Plug in power supply connector and apply power. The LED's corresponding to +5 Volts and -5 Volts should be illuminated. Reset board by pressing the MRST button. Connect a scope probe to TP25 and adjust R39 until the sync to blank amplitude is 286 mV. Connect a scope probe to TP19 and adjust R36 until the sync to blank amplitude is 286 mV. Connect a scope probe to TP21 and adjust R37 until the sync to blank amplitude is 286 mV. Connect a scope probe to TP23 and adjust R38 until the burst amplitude is 286 mV.
Power Supply Requirements
The TMB2193MS100 board requires 1.5 Amps from the +5 Volt power supply and 0.5 Amps from the -5 Volt power supply. Both the +5 Volt and -5 Volt supplies are connected to the input connector to supply the power requirements of any upstream board. The +5 Volt power supply not only drives TTL logic devices but it also provides the power and voltage references to the D/A's in the TMC2193. Therefore, it is recommended that a bench power supply be used with the cable lengths kept to a minimum.
4. 5. 6. 7. 8.
4
GENLOCK
CKDRIVE
CVBS[0..7] GHSYNC GVSYNC CKDRIVE GPXCK
GPXCK IXPXCK GPXCK IXPXCK
GMCU[0..6]
675MCLK 135MCLK MPXCK EPXCK FPXCK OPXCK
SCL SDA
PRODUCT SPECIFICATION
GENLOCK MPXCK
HEADERIN PD[0..23] ECVBS[0..9] OLENG[0..5] VSIN HSIN EPXCK EPXCK EMCU[0..3] EMCU[0..3] SCL SDA TMC2193 VSIN HSIN VSIN HSIN OLENG[0..5] OLENGI[0..5] HSOUT VSOUT PD[0..23] ECVBS[0..9] PD[0..23] ECVBS[0..9] DCVBS[0..9]
FPGA
TMC2193 DCVBS[0..9] HSOUT VSOUT OPXCK
HEADEROUT DCVBS[0..9] HSOUT VSOUT OPXCK SCL SDA RESET PGM_OUT PGM_OUT HEADEROUT
SCL SDA PGM_IN IXHSYNC IXVSYNC FMCU[0..7] IXPXCK FPGA FPXCK IXPXCK FPXCK IXPXCK
A[0..9] B[0..9] C[0..9] A_DEL[0..9]
HSOUT VSOUT
A[0..9] B[0..9] C[0..9] A_DEL[0..9] CVBS[0..7] 675MCLK GHSYNC GVSYNC IXHSYNC\ IXVSYNC\ A[0..9] B[0..9] C[0..9] A_DEL[0..9] CVBS[0..7] 675MCLK GHSYNC GVSYNC IXHSYNC IXVSYNC
MPXCK
RESET FRESET
HEADERIN FMCU[0..7]
POWER
Figure 1.
135MCLK MCU GMCU[0..6] FMCU[0..7] EMCU[0..3] PGM_OUT RESET FRESET PGM_IN VSOUT PGM_IN 135MCLK SCL SDA FRESET\ RESET\ MCU SCL SDA
GMCU[0..6]
{Schematic}
Raytheon Electronics - Semiconductor Division 5580 Morehouse Dr. San Diego, CA 92121 Title TOP Size B Date: Document Number TMB2193 Thursday, September 04, 1997 Sheet 1 of 12
65-B2193-02
Rev 0.9.0
TMB2193MS100
Preliminary Information
5
TMB2193MS100
PRODUCT SPECIFICATION
VCC
135MCLK U10A 74F74 5 U10B 74F74 9 10 PR 12 11 Q 6
PR
2 3
4
D
Q
D
Q
675MCLK
CLK CL
CLK CL Q 8
1
13
Y1 MPXCK OUT 5 E1 SELECT
PLACE COMPONENTS ON THIS PAGE CLOSE TO THE GENLOCK.
C3 0.1F
Preliminary Information
27MHz
GPXCK GPXCK VCC
VCC
VCC C1 0.1F
C2 0.1F
E2 SELECT U1A IXPXCK PASS 2 4 6 8 1 A1 A2 A3 A4 G 74F240 U1B Y1 Y2 Y3 Y4 18 16 14 12 MPXCK EPXCK FPCXK OPXCK MPXCK EPXCK FPXCK OPXCK
IXPXCK U2A 1 2
11 13 15 17 19
A1 A2 A3 A4 G 74F240
Y1 Y2 Y3 Y4
9 7 5 3
74F14
Raytheon Electronics - Semiconductor Division 5580 Morehouse Drive San Diego, CA 92121 (619) 457-1000 Title CKDRIVE.SCH Size B Date: Document Number TMB2193 Friday, February 07, 1997 Sheet 9 of 12 65-B2193-03 Rev 0.9.0
Figure 2.
6
VCC
VCC C4 0.1F R2 1K R3 1K R4 1K R5 1K C5 0.1F C6 0.1F C7 0.1F C8 0.1F C9 0.1F
PRODUCT SPECIFICATION
BYTE BLASTER
JP1
R1 1K
10 8 6 4 2 C10 0.1F U11 U4 3 4 OE nCS nCASC A_DEL2 DCLK CONF_DONE INIT_DONE 6 107 2 14 DCLK EPC1PC8 FMCU1 FMCU2 C19 0.1F FMCU0 A_DEL5 A_DEL9 DATA 2 1 77 76 35 74 MSEL0 MSEL1 nSTATUS nCONFIG C11 0.1F C12 0.1F C13 0.1F
9 7 5 3 1
C14 0.1F
HEADER 5X2
675MCLK
PD[0..23]
VCC
B[0..9]
106 3 142 141 144 143 11 7 nCE nCEO nWS nRS nCS CS RDYnBSY CLKUSR
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 PD4 PD3 PD2 PD1 PD0 OLENG5 OLENG4 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 TDI TDO TCLK TMS DEDIN DEDIN DEDIN DEDIN GCLK0 GCLK1 DEV_CLRn DEV_OE 116 114 113 112 111 110 109 108 105 4 1 34 C6 C8 IXHSYNC\ IXVSYNC\ 54 56 124 126
Figure 3.
A_DEL0 A_DEL1 A_DEL2 A_DEL3 A_DEL4 A_DEL5 A_DEL6 A_DEL7 A_DEL8 A_DEL9 A[0..9] FPXCK C7 PD10 PD11 125 55 122 128 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 GHSYNC GVSYNC GHSYNC GVSYNC IXHSYNC\ IXVSYNC\ IXHSYNC\ IXVSYNC\ IXPXCK FPXCK IXPXCK FPXCK A_DEL8 A_DEL7 A_DEL6 A_DEL4 A_DEL3 A_DEL1 A_DEL0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 8 9 10 12 13 17 18 19 20 21 22 23 26 27 28 29 30 31 32 EPF10K10TC144 8 9 10 12 13 17 18 19 20 21 22 23 26 27 28 29 30 31 32
A_DEL[0..9]
C[0..9]
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9
VSIN HSIN
VSIN HSIN
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23
OLENG[0..5]
ECVBS[0..9]
CVBS[0..7]
CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7
OLENG0 OLENG1 OLENG2 OLENG3 OLENG4 OLENG5
ECVBS0 ECVBS1 ECVBS2 ECVBS3 ECVBS4 ECVBS5 ECVBS6 ECVBS7 ECVBS8 ECVBS9
FMCU[0..7]
Raytheon Electronics - Semiconductor Division 5580 Morehouse Dr. San Diego, CA 92121 Title FPGA.SCH Size B Date: Document Number TMB2193 Thursday, September 04, 1997 Sheet 3 of 12 65-B2193-04 Rev 0.9.0
FMCU0 FMCU1 FMCU2 FMCU3 FMCU4 FMCU5 FMCU6 FMCU7
140 138 137 136 135 133 132 131 130 121 120 119 118 117 102 101 100 99 98 97 96 95 92 91 90 89 88 87 86 83 82 81 80 79 78 73 72 70 69 68 67 65 64 63 62 60 59 51 49 48 47 46 44 43 42 41 39 38 37 36 33
140 138 137 136 135 133 132 131 130 121 120 119 118 117 102 101 100 99 98 97 96 95 92 91 90 89 88 87 86 83 82 81 80 79 78 73 72 70 69 68 67 65 64 63 62 60 59 51 49 48 47 46 44 43 42 41 39 38 37 36 33 FMCU3 FMCU4 FMCU5 FMCU6 FMCU7 CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 CVBS0 GVSYNC GHSYNC OLENG3 OLENG2 OLENG1 OLENG0 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD9 PD8 PD7 PD6 PD5 VSIN HSIN ECVBS9 ECVBS8 ECVBS7 ECVBS6 ECVBS5 ECVBS4 ECVBS3 ECVBS2 C9 C5 C4 C3 C2 C1 C0 B9 B8 B7 B6 B5 B4 B3 B2
TMB2193MS100
Preliminary Information
7
Preliminary Information
VCC CVBS[0..7] CVBS[0..7] C20 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F C21 C22 C23 C24 C25 C26 C27 C28
+
2
C33 6.8pF GPXCK L1 10H C39 150pF C40 390pF C34 0.1uF C35 0.1uF C36 0.1uF
20MHz 19 20 NC NC JP3 JP4 A A A STUFF: A for TMC2072 B for TMC22071A TMC22071AKHC(2072KHC)_2 JP6 B JP7 B JP8 DGND B AGND GND JP5
1
GSA0
SDA
SDA
C37 0.1F
C38 0.1F
SCL
76 71 66 43 53 54 NC NC NC NC NC NC
82 DDS OUT 75 CBYP 77 PFD IN 45 PXCK 31 (BURL) 35 (FID0) 36 (FID1) 37 (FID2) 62 NC 59 NC 56 NC
STUFF EITHER C36 OR CR1
R15
GA0
33
GRW\
R16
GCS
33
Raytheon Electronics - Semiconductor Division H5 PTH H6 PTH H7 PTH H8 PTH 5580 Morehouse Drive San Diego, CA 92121 (619) 457-1000 Title GENLOCK.SCH 1 1 1 1 Size B Date: Document Number TMB2193 Monday, January 20, 1997 Sheet 2 of 12 65-B2193-05 Rev 0.9.0
2
8
U5 TP1 VID_IN R6 75 R7 75 10 11 12 13 14 15 NC NC NC NC NC NC TP2 GH TP3 GV TP4 GPXCK GHSYNC GVSYNC GPXCK NC NC NC NC NC NC NC 99 85 84 83 80 79 78 GHSYNC GVSYNC GPXCK C29 C30 R8 220 R10 GRESET\ 7 9 RESET D0 32 GHSYNC 33 GVSYNC GHSYNC GVSYNC GD0 33 VCC VCC GSA1 R13 4.75K R14 4.75K R12 4.75K INT VALID LDV 17 34 40 H1 H2 1 1 R/W (SDA) CS (SCL) A0 (SA0) (SA1) (SA2) 4 5 1 2 3 65 61 58 VIN1 VIN2 VIN3 + 22F/6.3V 22F/6.3V CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 21 22 23 24 25 28 29 30 CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 VCC R11 3.3K C31 0.1uF H3 1 86 94 91 93 PXCK SEL EXT PXCK CLK IN CLK OUT 88 COMP 70 VREF 68 RT 57 RB CR1 1.235V
TMB2193MS100
GMCU[0..6]
GMCU0 GMCU1 GMCU2 GMCU3 GMCU4 GMCU5 GMCU6
GRESET\ GCS GA0 GRW\ GD0 GSA1 GSA0
J1 BNC
1
R9 75
VCC
VCC
Y2
Figure 4.
C32 0.1F
OUT
5
20MCLK
PRODUCT SPECIFICATION
FRESET\
SDA
IXVSYNC\ IXHSYNC\ IXPXCK MPXCK HSOUT VSOUT A[0..9] SCL
1 A[0..9] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 A1 A0 A_DEL1 A_DEL0 A_DEL9 A_DEL8 A_DEL7 A_DEL6 A_DEL5 A_DEL4 A_DEL3 A_DEL2 A9 A8 A7 A6 A5 A4 A3 A2
PRODUCT SPECIFICATION
19
10 BIT FRAMESTORE
Figure 5.
Title Size B Document Number TMB2193 Thursday, September 04, 1997 Sheet 4 of 12 Rev 0.9.0 65-B2193-06 Date:
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
GND 2 3 4 5 6 7 8 9 VDD 11 12 13 14 15 16 17 18 GND 20 21 22 23 24 25 26 27 28 29 VDD 31 32 33 34 35 36 37 38 GND 40 41 42 43 44 45 46 47 VDD 49 50 51 52 53 54 55 56 57 58 VDD 60 61 62 63 64 65 66 67 68 69 70 71 GND A_DEL[0..9] P1 SIMM72 VCC A_DEL[0..9]
TMB2193MS100
Preliminary Information
9
Preliminary Information
-12V +12V -5V IXHSYNC\ R17 10K IXPXCK P2B PGM_IN IXPXCK FS_CONN FRESET IXVSYNC\ IXHSYNC\ IXHSYNC\ IXVSYNC\ IXPXCK IXHSYNC IXVSYNC IXPXCK A[0..9] {Value} A_DEL[0..9] HSOUT VSOUT MPXCK A[0..9] SCL SDA SCL SDA HSOUT VSOUT MPXCK P2C IXVSYNC\ -5V IXHSYNC\ IXVSYNC\ IXPXCK PGM_IN
10
IMASTER/SLAVE HSOUT VSOUT MPXCK A_DEL[0..9] PGM_IN SDA RESET\ SCL A[0..9] 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 EURO96F EURO96F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 C[0..9] 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 B[0..9] VSOUT HSOUT C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 MPXCK Raytheon Semiconductor - La Jolla 5580 Morehouse Drive San Diego, CA92121 (619) 457-1000 Title HEADERIN.SCH RESET\ Size B Date: Document Number TMB2193 Thursday, September 04, 1997 Sheet 10 of 12 65-B2193-07 Rev 0.9.0 SCL SDA
TMB2193MS100
VCC
P2A
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9
Figure 6.
EURO96F
VSOUT
HSOUT
MPXCK
FRESET\
SCL
SDA
PRODUCT SPECIFICATION
RESET\
PRODUCT SPECIFICATION
TMB2193MS100
96 WAY EDGE CONNECTIONS FROM THE TMC2193 BOARD
E3 SELECT PXCK PXCK4 U2B OPXCK 3 4 P3A 74F14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 EURO96M 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P3B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 EURO96M 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 P3C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 EURO96M PXCK\ -12V VCC -5V
+12V
PXCK4
DCVBS[0..9]
DCVS[0..9] DCVBS0 DCVBS1 DCVBS2 DCVBS3 DCVBS4 DCVBS5 DCVBS6 DCVBS7 DCVBS8 DCVBS9
VSOUT HSOUT
Preliminary Information
PGM_OUT
RESET\ SCL SDA
HSOUT
HSOUT
VSOUT
VSOUT
Raytheon Electronics - Semiconductor Division SDA SCL RESET\ SDA SCL RESET\ 5580 Morehouse Drive San Diego, CA92121 (619) 457-1000 Title HEADEROUT.SCH PGM_OUT Size B Date: Document Number TMB2193 Wednesday, January 22, 1997 Sheet 6 of 12 65-B2193-08 Rev 0.9.0
PGM_OUT
Figure 7.
11
TMB2193MS100
PRODUCT SPECIFICATION
VDD
D1 DIODE SCHOTTKY A_IN R18 75 Ohm D2 DIODE SCHOTTKY A_OUT
Preliminary Information
Raytheon Electronics - Semiconductor Division 5580 Morehouse Dr. San Diego, CA 92121 Title LPF.SCH Size A Date: Document Number TMB2193 Thursday, September 04, 1997 Sheet 11 of 12
65-B2193-09
Rev 0.9.0
Figure 8.
12
VCC VCC VCC R20 4K7 F BEAD R23 P4 10K 10K CAS_PROGEN SCL SDA R24 1OHM, 1/4W C RBUSEN U2D 9 UART 74F14 UART JP11 CASCADE INIT C42 0.1F PLACE NEAR STANDOFF 15-83-0064 SCL +5V SDA GND VCC 4 3 2 1 8 1 RESET\ 4 3 2 1 RXD TXD R22 4K7 JP10 2 D3 GREEN VCC FB3 R19 JP9
VCC
R21 10K
U2C
5
6
MRESET\
PRODUCT SPECIFICATION
74F14
C41 S1 10.0F/16V
MRST
VCC RESET\ R50 10K VCC FRESET\ C43 0.1F R51 10K R52 10K R53 10K R54 10K R55 10K R56 10K
RESET\
R49 10K
S2
FRESET\
1
Figure 9.
H9 H10 1 1 SCL SDA GCS GAO GRW\ GD0 ERESET\ EDCVBSEN\ ESA1 ESA0 43 42 41 40 39 38 37 36 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 NC NC NC NC 1 12 23 34 H4 135MCLK 135MCLK MRESET\ ERESET\ GRESET\ FRESET\ EDCVBSEN\ PROG0 PROG1 PROG2 PROG3 2 3 4 5 6 7 8 9 20 21 10 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL2 XTAL1 RST GRESET\ GCS GA0 GRW\ GD0 GSA1 GSA0 SCL SDA PGM_IN 135MCLK VSOUT
SA1 SA0 CAS ERS P0 P1 P2 P3 ESA1 ESA0 GSA1 GSA0 PROG0 PROG1 PROG2 PROG3
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
SW DIP-8
EMCU[0..3]
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
24 25 26 27 28 29 30 31
FMCU0 FMCU1 FMCU2 FMCU3 FMCU4 FMCU5 FMCU6 FMCU7 FMCU[0..7] FMCU[0..7]
EMCU0 EMCU1 EMCU2 EMCU3
RXD TXD VSOUT PGM_IN PGM_OUT CAS_PROGEN 1 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 EA/VPP ALE/PROG PSEN
PGM_OUT H11 1 35 33 32 VCC H12
GMCU[0..6]
11 13 14 15 16 17 18 19
PGM_OUT
GMCU0 GMCU1 GMCU2 GMCU3 GMCU4 GMCU5 GMCU6
SCL
U7 AT89C55 44 PIN PLCC
SDA
Raytheon Electronics - Semiconductor Division 5580 Morehouse Dr. San Diego, CA 92121 Title MCU.SCH Size B Date: Document Number TMB2193 Friday, September 19, 1997 Sheet 8 of 12 65-B2193-10 Rev 0.9.0
PGM_IN
135MCLK
VSOUT
TMB2193MS100
Preliminary Information
13
TMB2193MS100
PRODUCT SPECIFICATION
TP9 VDD P5V FB1 F BEAD JP12 1 2 3 POWER3 + C44 22F 35V N5V 1 2 + C48 22F 35V C50 0.1F 50V + C49 0.47F 35V C51 0.01F 50V 2 CR4 1N4004 C46 0.1F 50V + C45 0.47F 35V 1 C47 0.01F 50V 2 CR3 1N4004 2 CR2 RED LED DGND AGND GND CR5 ORANGE LED TP10 -5V VEE -5V 1 VDDA VCC +5V +5V
FB2 F BEAD
Preliminary Information
Ground Test Points TP11 GND TP12 GND TP13 GND TP14 GND TP15 GND
Raytheon Electronics - Semiconductor Division 5580 Morehouse Drive San Diego, CA92121 (619) 457-1000 Title POWER.SCH Size B Date: Document Number TMB2193 Thursday, January 23, 1997 Sheet 12 of 12 Rev 0.9.0
Figure 10.
14
1
PRODUCT SPECIFICATION
TMB2193MS100
VCC
R57 10K
R58 10K
R59 10K
R60 10K
R61 10K
R62 10K U9
AIN DIN CIN BIN JP14 A2XEN R41 D R42 D R43 D R44 D JUMPER JP15 B2XEN D IS150 OHM (1%) JUMPER JP16 C2XEN
1 24 13 12 4 9 16 21 7 18
AIN DIN CIN BIN A2X B2X C2X D2X NC1 NC2
AOUT DOUT COUT BOUT
5 20 17 8
AOUT DOUT COUT BOUT
Preliminary Information
ST-163E
JP20 JUMPER
JP21 JUMPER
JP22 JUMPER
JP23 JUMPER
JUMPER JP17 JUMPER JP18 JUMPER JP19 JUMPER DO NOT STUFF NC2EN NC1EN D2XEN R45 75 R46 75 R47 75 R48 75
ALL 1%
Title MMC Size A Date: Document Number TMB2193 Thursday, September 04, 1997 Sheet 7 of Rev 0.9.0 12 65-B2193-12
Figure 11.
15
Preliminary Information
VCC 39 54 72 96 U8 REFDAC TP18 DA1 AIN TP20 DA2 DIN TP22 DA3 BIN TP24 DA4 CIN {Schematic} 99 R_REF4 8 R_REF3 13 R_REF2 18 R_REF1 V_REF OL0 OL1 OL2 OL3 OL4 KEY C_BYB4 C_BYB3 C_BYB2 C_BYB1 3 6 11 16 CONNECT Cx TO VDDA PIN AND CBYPy PIN DIRECTLY C55 0.1uF C56 0.1uF C57 0.1uF C58 0.1uF 98 R31 10K Ohm R29 10K Ohm R33 8.25K Ohm 1 R37 10K Pot 2 R35 8.25K Ohm 1 COUT TP25 ODA4 BOUT TP23 ODA3 DOUT 1 J4 DAC2 1 2 J5 DAC3 1 2 J6 DAC4 2 TP21 ODA2 AOUT 1 J3 DAC1 2 MMC TP19 ODA1 19 A_IN A_OUT 1 J2 RDAC TP16 RDA 2 LPF {Schematic} TP17 ORDA
VDD VDD VDD VDD
3
TP26 PXCK TP29 HSIN R40 4K7 80 79 78 77 76 TP30 VSIN
TP27 TP28 VSOUT HSOUT
ECVBS0 ECVBS1 ECVBS2 ECVBS3 ECVBS4 ECVBS5 ECVBS6 ECVBS7 ECVBS8 ECVBS9 VDDA VDDA VDDA VDDA CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 CVBS8 CVBS9 PXCK RESET 83 FLD0 82 FLD1 81 FLD2 LINE0 LINE1 LINE2 LINE3 LINE4 EMCU0 95 ERESET\ 94
93 92 91 90 89 88 87 86 85 84
VDD JP13 R28 10K Ohm R32 8.25K Ohm 1 R34 8.25K Ohm 2 1 R36 10K Pot R30 10K Ohm
3
SCL SDA DGND DGND DGND DGND DGND AGND AGND AGND AGND
SCL SDA EMCU2 EMCU3
EDCVBSEN\ 57 58 59 60 61 ESA1 ESA0 62 DCVEN SER CS/SCL R/W/SDA A1/SA1 A0/SA0 26 40 53 71 97
D0 D1 D2 D3 D4 D5 D6 D7 TMC2193KHC
70 69 68 67 66 65 64 63
DCVBS0 DCVBS1 DCVBS2 DCVBS3 DCVBS4 DCVBS5 DCVBS6 DCVBS7 DCVBS8 DCVBS9
R27 VDD DCVBS[0..9] C54 0.1uF 2 1 DCVBS[0..9] 3.3K Ohm D4 1.235V
EMCU[0..3]
4 9 14 100
EMCU[0..3]
HSOUT VSOUT
STUFF EITHER C54 OR D4
VCC Raytheon Electronics - Semiconductor Division C65 0.1uF C66 0.1uF C67 0.1uF C68 0.1uF 5580 Morehouse Dr. San Diego, CA 92121 Title TMC2193.SCH Size B Date: Document Number TMB2193 Thursday, September 04, 1997 Sheet 5 of 12 65-B2193-13 Rev 0.9.0
PRODUCT SPECIFICATION
C61 0.1uF
C62 0.1uF
C63 0.1uF
C64 0.1uF
3
Figure 12.
EPXCK
HSIN VSIN HSOUT VSOUT EMCU1 HSIN VSIN PDC HSOUT VSOUT
56 55 73 74 75
1 2 3 4 5 6 7 8
R38 10K Pot 2
3
16
COMP/G/Y 15 Y/B/P_B 10 CH/R/P_R 5 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 52 51 50 49 48 47 46 45 44 43 42 41 38 37 36 35 34 33 32 31 30 29 28 27 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 COMP2 2 25 24 23 22 21 20 OLENG0 OLENG1 OLENG2 OLENG3 OLENG4 OLENG5 R39 10K Pot 2 VDD 1 7 12 17
TMB2193MS100
PD[0..23]
PD[0..23]
OLENGI[0..5]
OLENG[0..5]
ECVBS[0..9]
ECVBS[0..9]
PRODUCT SPECIFICATION
TMB2193MS100
Table 5. TMB2193MS100 Parts List Item 1 Quantity 48 Reference C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C19 C20 C21 C22 C23 C24C25 C26 C27 C28 C31 C32 C34 C35 C36 C37 C38 C42 C43 C46 C50 C54 C55 C56 C57 C58 C61 C62 C63 C64 C65 C66 C67 C68 C29 C30 C33 C39 C40 C41 C44 C48 C45 C49 C47 C51 R1 R2 R3 R4 R5 R6 R7 R9 R45 R46 R47 R48 R8 R10 R15 R16 R11 R12 R13 R14 R17 R21 R23 R24 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R18 R19 R20 R22 R40 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R41 R42 R43 R44 L1 FB1 FB2 FB3 CR1 D4 D1 D2 CR3 CR4 CR2 CR5 D3 JP1 MiniReel Ferrite Linear Technology Motorola MiniReel: 76-4004 Hewlett Packard Hewlett Packard Hewlett Packard Amp Part Number Manufacturer MiniReel: 605-611 Description 0.1mF (0805 FP)
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
2 1 1 1 1 2 2 2 5 7 1 3 1 3 18
Minireel MiniReel: 605-168 MiniReel: 605-315 MiniReel: 605-339 MiniReel: 642-810 MiniReel: 645-823 MiniReel: 641-647 MiniReel: 605-510 MiniReel: 615-410 MiniReel: 615-275 MiniReel: 615-822 MiniReel: 615-844 MiniReel: 615-844 MiniReel: 615-447 MiniReel: 615-510
22mF/6.3v (D FP) 6.8pF (0805 FP) 150pF (0805 FP) 390pF (0805 FP) 10.0mF/16V (B FP) 22mF/25v (D FP) 0.47mF/25v (A FP) 0.01mF (0805 FP) 1K (0805 FP) 75 (0805 FP) 220 (0805 FP) 33 (0805 FP) 3.3K (0805 FP) 4.75K (0805 FP) 10K (0805 FP)
Preliminary Information
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 35
1 1 3 1 4 4 4 4 1 3 2 2 2 1 1 1 1
MiniReel: 615-275 ROHM MiniReel: 615-848 MiniReel: 615-844 MiniReel: 615-849 MiniReel: 615-415 Bourns
75 (0805 FP) 1 OHM, 1/4W Carbon 4.7k (0805 FP) 3.3K Ohm (0805 FP) 10K Ohm (0805 FP) 8.25K Ohm (0805 FP) 10K Pot (SMT) 150 (0805 FP) 10uH (3225M FP) Ferrite Bead 1.235V Reference Diode Schottky Diode Rectifier Red LED Orange LED Green LED Header 5X2 17
TMB2193MS100
PRODUCT SPECIFICATION
Table 5. TMB2193MS100 Parts List (continued) Item 36 37 38 39 40 41 42 Quantity 6 1 1 1 1 6 1 1 1 3 1 1 21 Reference JP9 JP11 JP20 JP21 JP22 JP23 JP10 JP13 P1 JP12 J1 J2 J3 J4 J5 J6 P2 P3 P4 E1 E2 E3 S1 S2 TP1 TP2 TP3 TP4 TP9 TP10 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP28 TP29 TP30 TP11 TP12 TP13 TP14 TP15 U1 U2 U4 U5 U7 U8 U9 U10 U11 Y1 Y2 Part Number Manufacturer Amp Amp Amp Amp Beau Amphenol Amp Amp Molex Secma ITT Canon Alco Mouser Description 2 Pin Header 4 Pin Header 8 Pin Header 72 Pin Header Power, Plug Power, Socket BNC 96 Pin Euro Connector (Female) 96 Pin Euro Connector (Male) Rbus Connector SPDT Switch SMT Push Button Switch 8 Position DIP Switch Test Point
Preliminary Information
43 44 45 46 47 48
49 50 51 52 53 54 55 56 57 58 59 60
5 1 1 1 1 1 1 1 1 1 1 1
Bare Wire Motorola Motorola Atmel Fairchild Atmel Fairchild MMC Motorola Altera Ecliptec Ecliptec
Ground Point 74F240 74F14 Serial Eprom Genlock Microprocessor Encoder Video Filter ST-163E 74F74 FPGA 27MHz 20MHz
18
PRODUCT SPECIFICATION
TMB2193MS100
Table 6. INPUT 96 Way Connector (Female) row A 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 +5V D1 or R/V [bit 0] D1 or R/V [bit 1] D1 or R/V [bit 2] D1 or R/V [bit 3] D1 or R/V [bit 4] D1 or R/V [bit 5] D1 or R/V [bit 6] D1 or R/V [bit 7] D1 or R/V [bit 8] D1 or R/V [bit 9] Comp, G/Y, or Luma [bit 0] Comp, G/Y, or Luma [bit 1] Comp, G/Y, or Luma [bit 2] Comp, G/Y, or Luma [bit 3] Comp, G/Y, or Luma [bit 4] Comp, G/Y, or Luma [bit 5] Comp, G/Y, or Luma [bit 6] Comp, G/Y, or Luma [bit 7] Comp, G/Y, or Luma [bit 8] Comp, G/Y, or Luma [bit 9] Chroma or B/U [bit 0] Chroma or B/U [bit 1] Chroma or B/U [bit 2] Chroma or B/U [bit 3] Chroma or B/U [bit 4] Chroma or B/U [bit 5] Chroma or B/U [bit 6] Chroma or B/U [bit 7] Chroma or B/U [bit 8] Chroma or B/U [bit 9] GND 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 +12V GND GND +5V +5V +5V GND row B 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 +12V GND LOCK D1 RESET SCL GND SDA OE (output enable) BLANK (DAC) +5V GND PXCK GND PCK GND CREF GND VSYNC HSYNC HREF VREF ODD IN GND NTSC/PAL CLAMP pulse RGB row C
Analog Composite/luma
GND
Analog chroma
XEN GND XDIR XHSYNC XVSYNC XPXCK XRS [bit 3] XRS [bit 2] XRS [bit 1] XRS [bit 0] GND -5V -5V -5V GND PGM_IN -12V -12V IE (input enable) GND
Preliminary Information
19
TMB2193MS100
PRODUCT SPECIFICATION
Input Edge Connector Design Notes
Signal Flow FORWARD
1 Y/Composite LPF and Clamp Circuit TMC1185 TMC2242
1
1
1
High Quality LPF High Quality LPF High Quality LPF
65-B2193-14
EPROM
FPGA
TMC2072
10 bit ADCs TMC1185 Chrominance BPF and Clamp Circuit
Digital LPFs Decoder Input Logic 32 32
TMC3003 2:1 MUX TMC22153
Low Quality LPF Low Quality LPF Low Quality LPF
TMC2242
32 32 DC Supply SW1 +5V 0V -5V
SW1
SW2
Preliminary Information
Signal Flow BACKWARD
1.
Boards with different revision letters may not be compatible. Damage may occur if they are connected together! XPXCK is a two times pixel clock fed BACKWARD. XHSYNC and XVSYNC are timing reference signals fed BACKWARD. The MASTER/SLAVE signal states if a board is a MASTER or a SLAVE board. This signal is fed FORWARD. A MASTER board produces the PXCK, HSYNC, and VSYNC signals, and a SLAVE board expects to receive XPXCK, XHSYNC, XVSYNC, etc. XDIR is fed FORWARD and controls in which direction the XRS[3:0] data flows.
6.
2. 3. 4.
PGM_IN is a negative going pulse, logically ANDed with the onboard program start pulse, for initiating the programming sequence for components on that board. Care must be taken to ensure that multiple devices do not try to drive the RBUS at any given time. Minimum width of PGM_IN is 1uS. The RESET pin on the input edge connector should be connected directly to the RESET pin on the output connector. A link should be used to connect any pulse to the RESET line. The MASTER/SLAVE, XDIR, PGM_IN and RESET pins on the input edge connector should be connected to +5V through a 10k pull up resistor. The CLAMP signal is fed BACKWARD from a MASTER to a SLAVE board. The CLAMP signal should not be fed FORWARD.
7.
8.
5.
9.
20
PRODUCT SPECIFICATION
TMB2193MS100
Table 7. OUTPUT 96 Way Connector (Male) row A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 +5V D1 or R/V [bit 0] D1 or R/V [bit 1] D1 or R/V [bit 2] D1 or R/V [bit 3] D1 or R/V [bit 4] D1 or R/V [bit 5] D1 or R/V [bit 6] D1 or R/V [bit 7] D1 or R/V [bit 8] D1 or R/V [bit 9] Comp, G/Y, or Luma [bit 0] Comp, G/Y, or Luma [bit 1] Comp, G/Y, or Luma [bit 2] Comp, G/Y, or Luma [bit 3] Comp, G/Y, or Luma [bit 4] Comp, G/Y, or Luma [bit 5] Comp, G/Y, or Luma [bit 6] Comp, G/Y, or Luma [bit 7] Comp, G/Y, or Luma [bit 8] Comp, G/Y, or Luma [bit 9] Chroma or B/U [bit 0] Chroma or B/U [bit 1] Chroma or B/U [bit 2] Chroma or B/U [bit 3] Chroma or B/U [bit 4] Chroma or B/U [bit 5] Chroma or B/U [bit 6] Chroma or B/U [bit 7] Chroma or B/U [bit 8] Chroma or B/U [bit 9] GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 +12V GND GND +5V +5V +5V GND row B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 +12V GND LOCK D1 RESET SCL GND SDA OE (output enable) BLANK (DAC) +5v GND PXCK GND PCK GND CREF GND VSYNC HSYNC HREF VREF ODD IN GND NTSC/PAL CLAMP pulse RGB row C
Analog Composite/luma
GND
Analog chroma
XEN GND XDIR XHSYNC XVSYNC XPXCK XRS [bit 3] XRS [bit 2] XRS [bit 1] XRS [bit 0] GND -5V -5V -5V GND PGM_OUT -12V -12V IE (input enable) GND
Preliminary Information
21
TMB2193MS100
PRODUCT SPECIFICATION
Output Edge Connector Design Notes
Signal Flow FORWARD
1 Y/Composite LPF and Clamp Circuit TMC1185 TMC2242
1
1
1
High Quality LPF High Quality LPF High Quality LPF
65-B2193-14
EPROM
FPGA
TMC2072
10 bit ADCs TMC1185 Chrominance BPF and Clamp Circuit
Digital LPFs Decoder Input Logic 32 32
TMC3003 2:1 MUX TMC22153
Low Quality LPF Low Quality LPF Low Quality LPF
TMC2242
32 32 DC Supply SW1 +5V 0V -5V
SW1
SW2
Preliminary Information
Signal Flow BACKWARD
1.
Boards with different revision letters may not be compatible; damage may occur if they are connected together. XPXCK is a two times pixel clock fed BACKWARD. XHSYNC and XVSYNC are timing reference signals fed BACKWARD. The MASTER/SLAVE signal states if a board is a MASTER or a SLAVE board. This signal is fed FORWARD. A MASTER board produces the PXCK, HSYNC, and VSYNC signals, and a SLAVE board expects to receive XPXCK, XHSYNC, XVSYNC, etc. XDIR is fed FORWARD and controls in which direction the XRS[3:0] data flows. PGM_OUT negative going signal pulse for initiating programming of down stream boards, generated once the devices on the board have been programmed. Care must be taken to ensure that multiple devices do not try to drive the RBUS at any given time. The Minimum width of PGM_OUT is 1uS. The RESET pin on the output edge connector should be connected directly to the RESET pin on the input connector. A link should be used to connect any pulse to the RESET line.
8.
The MASTER/SLAVE, XDIR, PGM_OUT and RESET pins on the output edge connector should be connected to +5V through a 10k pull up resistor. The CLAMP signal is fed BACKWARD from a MASTER to a SLAVE board. The CLAMP signal should not be fed FORWARD.
2. 3. 4.
9.
Related Products
* * * * * TMB22153MS101 Decoder demonstration board TMB1185MS102 ADC demonstration board TMB0000UG100 RBUS Interface TMB0001MS100 Parallel D1 interface board Raydemo software
5. 6.
7.
22
PRODUCT SPECIFICATION
TMB2193MS100
Notes:
Preliminary Information
23
TMB2193MS100
PRODUCT SPECIFICATION
Ordering Information
Product Number TMB2193MS100 Temperature Range 25C Speed Grade 27 MHz Screening Commercial Package 4" by 5" Printed Circuit Board Package Marking TMB2193MS100
A schematic database is available in OrCADTM format. Contact the factory. The TMB2193MS100 Demonstration Board, design documentation, and software are provided as a design example for the customers of Fairchild. Fairchild makes no warranties, express, statutory, or implied regarding merchantability or fitness for a particular purpose.
FCC Compliance
Preliminary Information
This device has not been approved by the Federal Communications Commission (FCC). This board is intended for the evaluation of Fairchild products only. This device is not and may not be offered for sale or lease or sold or leased until the approval of the FCC has been obtained.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 6/3/98 0.0m 002 Stock# DS7TMB2193 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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